The present invention relates to a method of manufacturing interpoly dielectric layer to improve reliability of flash memory devices. More particularly, it is related to a method of manufacturing flash memory devices by semi-atmospheric pressure chemical vapor deposition (SAPCVD) and tetra-ethyl-ortho-silicate (TEOS) reactants.
Flash memory is a semi-conductor technique developed according to RAM product of computer. Flash memory is a solid-state storage system, which consumes less-power to change inner data quickly by using the efficient block way, and flash memory retains data without any additional power.
Flash memory and other solid-state memories, for example, read only memory (ROM), static/dynamic random access memory (SRAM/DRAM), and electrically erasable programmable read only memory (EEPROM) are applied widely.
Among these solid-state memories, the flash memory is the best storage system with high quality since the flash memory has characteristics of non-volatile, rewritable, high density and stability.
FIG. 1 is a cross-section view of a conventional flash memory device. The structure of the conventional flash memory device includes a substrate 10, and a source region 12, a drain regain 14, and a channel region 16 located in the substrate 10, and a stacked gate structure 18 located on the substrate 10. Herein the stacked gate structure 18 further includes a tunnel oxide layer 20, a floating gate 22, an interpoly dielectric layer 24, and a control gate 26. The floating gate 22 and the control gate 24 are usually composed of polysilicon, and the interpoly dielectric layer 24 is composed of multi-insulated layers, i.e. oxide/nitride/oxide (ONO) structure. The ONO structure 24 includes a bottom oxide layer 28, a nitride layer 30, and a top oxide layer 32. When current flows through the channel region 16 of the flash memory device to electrically connect the source region 12 and the drain region 14, meanwhile electric field is applied to the stacked gate structure 18.
To be the insulation structure between the floating gate 22 and the control gate 24, the ONO structure 24 has to be high reliability. For example, if the top oxide layer 32 is too thick, the needful conductive voltage may be increased. Otherwise, if the top oxide layer 32 is too thin, in the flash memory the current leaks out easily so that the memory ability and storage time of charges also decreased. Accordingly, it is important to control the thickness of the top oxide layer. In addition, if the nitride layer is too thin, current leakage may be happened between floating gate 22 and control gate 24, and charge storage time is also shortened.
The conventional method of manufacturing the interpoly dielectric layer 24 ONO structure of flash memory device is to oxidize the nitride layer directly by wet thermal oxidation. For example, under 950xc2x0 C. vapor circumstance the process of oxidizing the nitride layer about 40 minutes to transform a portion of the nitride layer into the top oxide layer 32.
The other conventional method of manufacturing the interpoly dielectric layer 24, ONO structure of flash memory device is to form an oxide layer on the nitride layer, for example, by low-pressure vapor deposition (LPCVD). The LPCVD process is performed under the circumstance, includes: lower temperature between about 600xc2x0 C. and about 850xc2x0 C. and higher pressure between about 400 mTorr and about 750 mTorr; injecting reactive gases (as SiH4 and N2O) and inert gas or N2 to form SiO2 layer; and performing a rapid thermal anneal (RTA) process to nitrify the oxide layer for about 40 seconds to 80 seconds under a temperature between about 700xc2x0 C. and 950xc2x0 C. in order to density the oxide layer or reduce defects and charge trap formed on the top oxide layer of flash memory devices. Since the increased temperature decomposes N2O to N2 and reactive oxygen molecules, the oxygen molecules will diffuse to oxygen lattice""s vacancies of LPCVD oxide layer resulting to density decreasing and current leakage.
In the above interpretation, the conventional method of wet thermal oxidation tends to react excess nitride, so that the nitride layer may be too thin resulting charge leakage. In the other hand, long reactive time and high reaction temperature also introduce defects and charge traps and decrease the reliability of tunnel oxide layer.
In the above interpretation, the conventional method of LPCVD process is more complex and consumes more gases by repeating decompression and gas exhausting to maintain low-pressure circumstance. Molecules in low-pressure move in the form of molecular flow, so that the collision frequency between molecules is very low and it is therefore very hard to produce the collisions needed to induce CVD process. Hence, the deposition rate of film is slow and takes long time. Moreover the turbulent flow also induces dust in reaction chamber so that the deposition quality is influenced. Furthermore, the SiH4 reactant is reacted by homogeneous nucleation so that the step coverage ability of this conventional process is poor because of the surface pollution of the reactor by dust.
Therefore, one aspect of the present invention is to provide a semi-atmospheric pressure chemical vapor deposition to improve the disadvantages of long thermal budget and uncontrolled thickness, which are caused from conventional wet thermal oxidation under high temperature. The present invention also improves the problems caused by repeating decompression, low collision frequency and turbulent flow.
Other aspect of the present invention is that using tetra-ethyl-ortho-silicate (TEOS) reactants to form the oxide layer to improve the disadvantage of dusted pollution caused from SiH4.
According to the above aspects, the present invention combines SAPCVD process and TEOS reactants to decrease defect and interface trap. Wherein SAPCVD includes the step of reacting TEOS reactants with oxygen under temperature between about 600xc2x0 C. and 750xc2x0 C. and pressure between about 340 Torr and 550 Torr.